| Device | W5500 | W5200 |
|---|---|---|
| 制程 | 0.13um | 0.18um |
| 封裝 | 48 LQFP (7*7 mm^2) | 48 QFN (7*7 mm^2) |
| IO 電壓 / 核心電壓 | 3.3V / 1.2V | 3.3V / 1.8V |
| sockets數(shù)量 | 8 ea | 8 ea |
| SPI Frame | ADD1|ADD2|Control|Data0|Data1… | ADD1|ADD0|OP+LEN1|LEN0|Data… |
| 8bit |8bit |8bit |8bit | 8bit | 8bit |8bit |1bit +7bit |8bit | 8bit | |
| Control 1 byte (Block selection, Read/Write selection, SPI mode selection) | OP Code 1 bit (Read/Write Selection) | |
| No Data Length field | Data Length 15bit | |
| Memory Access | TX Memory and RX Memory can be accessible as general data memory. | TX Memory can be accessible as general data memory. |
| MCU總線(xiàn)接口 | SPI | SPI / Indirect bus mode |
| Regulator Related Circuit | LDO output pin needs the capacitor. No need to supply the chip power (1.2V). | LDO output voltage (1.8V) must be applied to the chip power (1.8V) at the outer side of the chip package. |
| PHY Power Down Setting | PHY's power down mode can be set by configuring PHY Register. | PHY's power down mode can be set by external pin. |
| WOL Function | WOL over UDP Support | WOL over Ethernet Support |
| PHY Mode Setting | PHY mode can be set by Firmware | |
| Status LED | 4 LEDs (SPD / DUP / ACT / Link) | 3 LEDs (SPD / DUP / Link) |
| PHY Auto MDIX Function | Not Support | Support |
| Operating Current @100Mbps Full Link | Typical 132mA | Typical 160mA |
013年9月1日WIZnet宣布新產(chǎn)品W5500發(fā)布生產(chǎn)，最新增加到他們久經(jīng)市場(chǎng)驗(yàn)證的W5xxx行列。早期的W5100和W5200芯片取得了成功，并帶來(lái)了硬件TCP/IP協(xié)議處理低成本應(yīng)用的利處。W5500發(fā)揚(yáng)了早期芯片的所有主要特征。
- 全功能10/100以太網(wǎng)MAC&PHY
-全硬件TCP/IP協(xié)議處理
-8個(gè)獨(dú)立socket
-32KB RAM緩存
